ATLASS project lies on five main technological objectives to serve six major outcomes, along four main technology development routes as shown in the picture above.
The five main objectives are:

 _ Develop multifunctional materials with optimized performances and optimized printability

 _ Develop and optimize high resolution printing processes towards nanoscale

 _ Develop and integrate in-line automatic optical inspection and yield management

 _ Scale-upe the materials and high resolution printing technologies to demonstrate it

 _ Demonstrate the benefits of the technology on specific use cases

In order to properly achieve these objectives and provide a full evaluation of technological capability, the ATLASS project is divided in four “technological routes”. The “technological routes” approach implemented here is based on a “continuous improvement” cycle model such as one developed in semiconductor industry. It enables to cope with the long development cycle inherent to electronic manufacturing hierarchy and allows extension of the technology up to the system level while preparing in parallel the development of elementary modules for next technological generation. This scheme will enable for each ATLASS route to demonstrate specific outcomes:

AT_base” route (March 2015 to February 2017): The main scope of this route is to provide a baseline for system performance, manufacturing cost and throughputs evaluation on conventional TOLAE process, enabling clear figures for the benchmark of ATLASS developments. This route employs the reference OTFT process available at Flexenable for the fabrication of a first version of a sensor application. This route starts at the system level with design and fabrication of circuits and demonstrators. Moreover this route enables early validation of Sensor front Plane.

“AT_4000” route: Shown by the light-grey arrow and the light-grey horizontal blocks, this is the main ATLASS route for printing & OTFT development and is used for the evaluation of process benefits and demonstration of the high impact applications enabled by ATLASS. The AT_4000 route is covered by all project activities and run from initial delivery of materials from Merck, until fabrication of the applicative demonstrations at the end of the project. This route is used to set up the ATLASS demonstration roll-to-roll and sheet-to-sheet printing processes with a minimum OTFT feature size of 4µm, integrate them into a unique process flow and assess thin film transistor performance; in parallel, the set-up of AOI hardware, software, and defect capture recipes is performed on this route, allowing correlation with yield results from test circuits. At first stage engineering mask-sets, PEM_4000 (Printability Evaluation Module), and TEM_4000 (Transistor Evaluation Module) are designed with various test structures in order to engineer the ATLASS printing tools (NIL moulds, Gravure cylinders), printing processes, AOI defectivity hardware and  recipes, electrical test of OTFTs and basic circuits (i.e. arrays of OTFTs) for yield evaluation. After electrical performance optimization and freeze of the process flow at mid-project, the OTFT for AT_4000 route are modelled for the set-up of Design Tool-kit enabling simulation assisted design of the circuits needed for the four ATLASS application demonstrations.These circuits referred as CEM_4000 (Circuit Evaluation Modules) will be the designed, simulated, and fabricated in two successive iteration loops. Lamination and assembly with ATLASS “front-planes” sensing foil and displays and validation in applicative scenarios will finalize this route.

 “AT_2000” route: first ATLASS shrink route from mid-project until the end, is shown with the mid-grey diagonal arrow and horizontal blocks.  In this route ATLASS feature size is reduced and targets a minimum feature size of 2µm. The objective of this process flow is to shrink the ATLASS design rules, together with inserting the new High Performance materials developed by ATLASS first activity (WP1). This route, covered only by the first four activities (WP1, WP2, WP3 and WP4), is tested up to the OTFT level, AOI level, and Yield level. The results are assessed using the PEM_2000 and TEM_2000 “shrink” PEM and TEM test structures. AT_2000 validates the capability of designing ink materials and printing forms for shrink feature sizes at demonstration level and thanks to increase in resolution and performance (Channel at 1.5µm, dielectric at 200 nm, mobility >1 cm²/V/s) enables demonstration of very high performance devices with low voltage operation (<5V).  

“AT_800” route: Second Shrink Route in the last months of the project, is shown by the dark-grey arrows and blocks. In this route ATLASS targets a minimum feature size to 800nm. Beyond the“AT_2000” route, ATLASS will evaluate here the ultimate scaling of each ATLASS printing process; this prospective study will be led using “nano-scale” test structures laid-out on the PEM_800 mask set, and assessed only at the “inspection” level and defectivity level (no electrical test, no yield). This route validates the printability of up-scaled batches of materials issued from WP1, and highlight any critical issues for next generations of OTFT printing technology (materials, printing forms and processes, defectivity control). It is covered by WP 1, 2, 3 and 4.



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